module draw_picture(
	input clk, 
	input reset_n,
	input [15:0]picture_rd_data,
	input init_done,
	input write_done_sig,
	output reg clk_r,
   input  [19:0]rd_addr,
	input req_b,
	output reg[1:0]sig,//sig=2'b10传送的为地址命令 sig=2’b01传送为为数据
	output reg[15:0]write_data,
	output reg wr_rd_sig,//wr_rd_sig=1 写 wr_rd_sig=0 读
   output reg write_read_stop,
	output reg ready

);


	
	`define     IDLE    2'b00
	`define     DATA    2'b01
	`define     CMD     2'b10
	
	
	
	parameter delay = 3'd1;              //20ns延时
					
	reg[2:0]cnt;
	reg start;
	always@(posedge clk or negedge reset_n)
	begin
		if(!reset_n)
			cnt <= 3'd0;
		else if((cnt == delay) || (start == 1'b0))
			cnt <= 3'd0;
		else if(start)
			cnt <= cnt + 1'b1;			
	end
			

	
	/*********************************************************************/
	reg [8:0]j;
   reg [15:0]d_data;
	reg  [19:0]d_addr;
	
	
	/*****************************开窗数据**********************************/

	reg[15:0]x_r,y_r;//x列起始,y行起始	


	

	parameter length = 16'd240;
	parameter width = 16'd320;//显示图形的列宽度
	parameter len = 16'd1;//列宽度
	parameter wid = 16'd1;//行宽度
	parameter pixel_num = 17'h257f  ;  //像素点个数  9600-1
	parameter lcd_pixel_num = 17'h12c00  ;  //LCD像素点个数  76800
	
	
	
	/***********************初始化*****************************************/
	always@(posedge clk or negedge reset_n)
	if(!reset_n)
	begin 
		j <= 9'd0;
		sig <= `IDLE;
		start <= 1'b0;	
		write_read_stop<= 1'b1; //停止读写
		x_r <= 16'd0;
		y_r <= 16'd0;
		ready <= 1'b0;
	end
	else 
		case(j)
		
       0: if(init_done) begin j  <= j + 1'b1; write_read_stop <= 1'b0;  end
		 else begin j  <= j ;end
		
		/*************************开始显示图片****************************************/
		1: begin  ready <= 1'b1;  j <=  j + 1'b1; end
		
		2:if((cnt == delay) && req_b)   j <=  j + 1'b1;
		else begin j <=  j;sig <= `IDLE;start <= 1'b1;end
		
		//获取地址，数据等
		3:begin d_data <= picture_rd_data;  d_addr <=  rd_addr; j <=  j + 1'b1; end
		
		//开始写操作，禁止读入数据,计算要写的像素的行列
		4:begin ready <= 1'b0;  x_r <=  d_addr%length;  y_r <= d_addr / length; j <=  j + 1'b1;  end
		
      //写地址
		//CMD:2A		
		5:if(write_done_sig)j <=  j + 1'b1;
		else begin start <= 1'b0;sig <= `CMD;write_data <= 16'h002a; wr_rd_sig <= 1'b1; end//行范围
		
		6:if(cnt == delay)j <=  j + 1'b1;
		else begin j <=  j;sig <= `IDLE;start <= 1'b1;end
	
	   7:if(write_done_sig)j <=  j + 1'b1;
		else begin start <= 1'b0;sig <= `DATA;write_data <= (x_r>>8);end//行起始高8位
		
		8:if(cnt == delay)j <=  j + 1'b1;
		else begin j <=  j ;sig <= `IDLE;start <= 1'b1;end
		
		9:if(write_done_sig)j <=  j + 1'b1;
		else begin start <= 1'b0;sig <= `DATA;write_data <= (x_r-((x_r>>8)<<8));end//行起始低8位	
		
		10:if(cnt == delay)j <=  j + 1'b1;
		else begin j <=  j ;sig <= `IDLE;start <= 1'b1;end
		
		11:if(write_done_sig)j <=  j + 1'b1;	
		else begin start <= 1'b0;sig <= `DATA;write_data <= ((x_r+len-1)>>8);end//行终止高8位
		
		12:if(cnt == delay)j <=  j + 1'b1;
		else begin j <=  j ;sig <= `IDLE;start <= 1'b1;end
		
		13:if(write_done_sig)j <=  j + 1'b1;
		else begin start <= 1'b0;sig <= `DATA;write_data <= ((x_r+len-1)-(((x_r+len-1)>>8)<<8));end//行终止低8位
		
		14:if(cnt == delay)j <=  j + 1'b1;
		else begin j <=  j ;sig <= `IDLE;start <= 1'b1;end
		
		//CMD:2b
		15:if(write_done_sig)j <=  j + 1'b1;
		else begin start <= 1'b0;sig <= `CMD;write_data <= 16'h002b;end//行范围
		
		16:if(cnt == delay)j <=  j + 1'b1;
		else begin j <=  j ;sig <= `IDLE;start <= 1'b1;end
		
		17:if(write_done_sig)j <=  j + 1'b1;
		else begin start <= 1'b0;sig <= `DATA;write_data <= (y_r>>8);end//行起始高8位
		
		18:if(cnt == delay)j <=  j + 1'b1;
		else begin j <=  j ;sig <= `IDLE;start <= 1'b1;end
		
		19:if(write_done_sig)j <=  j + 1'b1;
		else begin start <= 1'b0;sig <= `DATA;write_data <= (y_r-((y_r>>8)<<8));end//行起始低8位
		
		20:if(cnt == delay)j <=  j + 1'b1;
		else begin j <=  j ;sig <= `IDLE;start <= 1'b1;end
		
		21:if(write_done_sig)j <=  j + 1'b1;	
		else begin start <= 1'b0;sig <= `DATA;write_data <= ((y_r+wid-1)>>8);end//行终止高8位
		
		22:if(cnt == delay)j <=  j + 1'b1;
		else begin j <=  j ;sig <= `IDLE;start <= 1'b1;end
		
		23:if(write_done_sig)j <=  j + 1'b1;
		else begin start <= 1'b0;sig <= `DATA;write_data <= ((y_r+wid-1)-(((y_r+wid-1)>>8)<<8));end//行终止低8位
		
		24:if(cnt == delay)j <=  j + 1'b1;
		else begin j <=  j ;sig <= `IDLE;start <= 1'b1;end
		
      //CMD:2c		
		25:if(write_done_sig)j <=  j + 1'b1;
		else begin start <= 1'b0;sig <= `CMD;write_data <= 16'h002c;end
		
		26:if(cnt == delay)j <=  j + 1'b1;
		else begin j <=  j ;sig <= `IDLE;start <= 1'b1;end
		
		27:if(write_done_sig)j <=  j + 1'b1;
			else begin start <= 1'b0;sig <= `DATA;write_data <= d_data;end//5:6:5 RGB 颜色数据
			
		28:if(cnt == delay)j <=  j + 1'b1;
		else begin j <=  j ;sig <= `IDLE;start <= 1'b1;end
		
		//写完 ready拉高，回到等待状态
		29:begin j <=  9'd1;  end 
	
		
		
		
		/*************************结束显示图片****************************************/
		
		
		
		
	endcase
	




endmodule
